The invention relates to a technique effectively applied to a device structure and a manufacturing technology of power semiconductor devices (or semiconductor integrated circuit devices), such as an insulated gate bipolar transistor (IGBT) or a diode.
Japanese Unexamined Patent Publication No. 2004-193212 (Patent Document 1) discloses a technique that provides an n+-type region at some midpoint of an n−-type drift region in a punch-through type IGBT or the like so as to suppress vibrations of voltage and current waveforms at the time of turn-off.
Japanese Unexamined Patent Publication No. 2001-77357 (Patent Document 2) discloses a technique that provides an n−-type intermediate region and a low lifetime region included therein, between a p+-type collector region and an n+-type field stopping region in a punch-through IGBT or the like so as to achieve low tail current characteristics or the like.
Japanese Unexamined Patent Publication No. 2008-85050 (Patent Document 3) or U.S. Pat. No. 7,776,660 (Patent Document 4) corresponding thereto discloses a technique for an IGBT or the like with a field stopping region, using a silicon single crystal wafer formed by a floating zone (FZ) method. The technique involves using crystal defects remaining due to ion implantation as a lifetime killer upon annealing after performing the ion implantation for formation of a collector from its backside.